Complementary symmetry metal oxide silicon integrated circuits (CMOS ICs) have been powered by the same power supply as other circuits supported by circuit boards on which they reside.
With the increasing number of gates on modern ICs, smaller geometry CMOS processes have become vital to maintain area and power consumption at acceptable levels. However, the transition to smaller geometry processes is coupled with a reduction in the gate oxide thickness. The susceptibility of the thinner gate oxide to damage from high voltages precludes the use of traditional 5V logic level CMOS input signals. This mandates the need for circuitry to bridge the interface between mixed voltage levels.
As the state of the art transitions to lower voltages, there are many legacy requirements that mandate the ability of ICs to handle mixed supply voltage inputs, e.g. 5V referenced PECL levels passing to 3.3V ICs, 3.3V referenced PECL levels passing to 2.5V ICs. Circuits are needed to receive these higher voltage input signals and reduce them to acceptable levels so that they can be handled by the lower voltage ICs.
Recently, a good deal of effort has been directed to a method interfacing higher voltage digital inputs with lower voltage ICs. These methods do not allow for the retention of the small signal content. Inputs are read as logic high or logic low. The need to reduce common-mode voltage levels on small signal inputs has also become necessary.
One solution to the above problems is to AC-couple the high voltage input to the low voltage IC. However AC-coupling has a disadvantage in that it causes base line wander due to the small time constant of the coupling capacitor.
Additionally, the component count increases due to both the coupling capacitors and the resistors required to set the common-mode levels. The common-mode can be set internally, removing the requirement for off-chip biasing resistors. However this forces the use of an internal reference generator, increasing cost.
A circuit that would provide translation between higher voltage AC signals to lower voltage ICs, such as between 5.0 volts and 3.3 volts, or between 3.3 volts and 2.5 volts, without attenuating the AC signals or introducing excess distortion, and at minimum cost is thus highly desirable. Further, the circuit should not sacrifice electrostatic discharge robustness, and it should not require AC-coupling.